/*
  ******************************************************************************
  * @file    apt32f172_tc3_ctc.h
  * @author  APT AE Team
  * @version V1.12
  * @date    2018/03/08
  ******************************************************************************
  *THIS SOFTWARE WHICH IS FOR ILLUSTRATIVE PURPOSES ONLY WHICH PROVIDES 
  *CUSTOMER WITH CODING INFORMATION REGARDING THEIR PRODUCTS.
  *APT CHIP SHALL NOT BE HELD RESPONSIBILITY ADN LIABILITY FOR ANY DIRECT, 
  *INDIRECT DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT OF 
  *SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION 
  *CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.AND APT CHIP RESERVES 
  *THE RIGHT TO MAKE CHANGES IN THE SOFTWARE WITHOUT NOTIFICATION
  ******************************************************************************
  */

/* Define to prevent recursive inclusion -------------------------------------*/ 
#ifndef _apt32f172_tc3_ctc_H
#define _apt32f172_tc3_ctc_H

/* Includes ------------------------------------------------------------------*/
#include "apt32f172.h"

/******************************************************************************
************************** CTC Registers Definition ***************************
******************************************************************************/
/** @addtogroup CTC Registers RST  Value
  * @{
  */
#define 	CTC_IDR_RST         (0x0001002D)    			/**< IDR reset value     */
#define   	CTC_CSSR_RST        (0x00000001)				/**< CSSR reset value    */
#define 	CTC_CEDR_RST	 	(0x00000000)				/**< CEDR reset value    */	
#define 	CTC_SRR_RST		 	(0x00000000)				/**< SRR reset value     */
#define 	CTC_CR_RST			(0x00000030)				/**< CR reset value      */
#define 	CTC_PRDR_RST		(0x00000001)				/**< PRDR reset value    */
#define 	CTC_TIMDR_RST		(0x00000000)				/**< TIMDR reset value   */
#define 	CTC_IMCR_RST		(0x00000000)				/**< IMCR reset value    */
#define 	CTC_RISR_RST		(0x00000000)				/**< RISR reset value    */
#define 	CTC_MISR_RST		(0x00000000)				/**< MISR reset value    */
#define 	CTC_ICR_RST		 	(0x00000000)				/**< ICR reset value     */
/**
  * @brief  CTC INT  
  */  
typedef enum
{
	CTC_INT_PEND    =     (0x01ul<<0),     
	CTC_INT_OVF    	=     (0x01ul<<1)      
}CTC_INT_TypeDef;

/**
  * @brief  CTC BUZZ Freq set  
  */  
typedef enum
{
	CTC_BUZZ_Freq_500Hz		=	(0x00ul<<1),
	CTC_BUZZ_Freq_1kHz		=	(0x01ul<<1),
	CTC_BUZZ_Freq_2kHz		=	(0x02ul<<1),
	CTC_BUZZ_Freq_4kHz		=	(0x03ul<<1)
}CTC_BUZZ_Freq_TypeDef;

/**
  * @brief  CTC Count Period set  
  */  
typedef enum
{
	CTC_Count_Period_4ms		=	(0x00ul<<3),
	CTC_Count_Period_16ms		=	(0x01ul<<3),
	CTC_Count_Period_63ms		=	(0x02ul<<3),
	CTC_Count_Period_125ms		=	(0x03ul<<3),
	CTC_Count_Period_250ms		=	(0x04ul<<3),
	CTC_Count_Period_500ms		=	(0x05ul<<3),
	CTC_Count_Period_1s			=	(0x06ul<<3),
	CTC_Count_Period_PRDR		=	(0x07ul<<3)
}CTC_Count_Period_TypeDef;

/**
  * @brief  CTC Count Mode set  
  */  
typedef enum
{
	CTC_Count_Mode_set_Normal	=	(0x00ul<<6),
	CTC_Count_Mode_set_Period	=	(0x01ul<<6)
}
CTC_Count_Mode_set_TypeDef;

/**
  * @brief  CTC CLK Source  
  */  
typedef enum
{
	CTC_CLK_Source_set_EMOSC	=	0,
	CTC_CLK_Source_set_ISOSC	=	1
}CTC_CLK_Source_set_TypeDef;
/*****************************************************************************
******************** CTC External Functions Declaration **********************
******************************************************************************/
extern void CTC_RESET_VALUE(void);
extern void CTC_CONFIG(void);
extern void CTC_Clk_CMD(FunctionalStatus NewState);
extern void CTC_Int_Enable(void);
extern void CTC_Int_Disable(void);
extern void CTC_Wakeup_Enable(void);
extern void CTC_Wakeup_Disable(void);
extern void CTC_INT_CMD(CTC_INT_TypeDef CTC_INT_X , FunctionalStatus NewState);
extern void CTC_IO_Init(U8_T CTC_IO_G );
extern void CTC_Config(CTC_CLK_Source_set_TypeDef CTC_CLK_Source_set_X , CTC_BUZZ_Freq_TypeDef CTC_BUZZ_Freq_X ,
			CTC_Count_Period_TypeDef CTC_Count_Period_X );
extern void CTC_Start(void);
extern void CTC_stop(void);
extern void CTC_SoftReset(void);

#endif   /**< apt32f172_tc3_ctc_H */

/******************* (C) COPYRIGHT 2018 APT Chip *****END OF FILE****/


